The ongoing block transfer will be completed, but no new transfers will be requested. Note: Disabling an active channel will interrupt the DMA operation. Note: Completion of the software reset must be checked in DMASTAT.CH0_ACTIVE and DMASTAT.CH1_ACTIVE. This register field indicates if DMA channel 0 is active or not. This register field indicates if DMA channel 1 is active or not. Reflects possible transfer errors on the AHB port. Note: Writing a non-zero value to this register field starts the transfer if the channel is enabled by setting DMACH0CTL.EN. During operation, it contains the last updated value of the DMA transfer length after being sent to the master interface. Holds the last updated external address after being sent to the master interface.ĭuring configuration, this register contains the DMA transfer length in bytes. If both channels have the same priority access of the channels to the external port is arbitrated using a Round Robin scheme. Writing any other value than the reset value may result in undefined behavior.Ī channel with high priority will be served before a channel with low priority in cases with simultaneous access requests. Software should not rely on the value of a reserved. TOP:CRYPTO Register Descriptions TOP: CRYPTO:DMACH0CTL Address Offset Crypto core with DMA capability and local key storage TOP: CRYPTO Register Summary
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